影响高速PCB插入损耗设计因子研究  

Research on design factors affecting insertion loss of high speed PCB

作　　者：张志超 向参军 彭镜辉 李超谋 Zhang Zhichao;Xiang Canjun;Peng Jinghui;Li Chaomou

机构地区：[1]广州广合科技股份有限公司,广东广州510730

出　　处：《印制电路信息》2021年第S01期29-37,共9页Printed Circuit Information

摘　　要：随着通讯技术的快速发展,PCB行业内对高速电路板的信号完整性研究也越来越多,如在测试方法及制造工艺方向的研究,以确保有更精准的产品损耗数据来保证产品质量;在产品工程设计阶段,受材料选用、介质层厚度设计、线宽/间距设计、信号线厚度及长度设计差异影响,制造出来的电路板损耗表现也有较大差异。文章通过探究上述因素对电路板信号完整的影响规律,以期在工程设计上能获得信号完整性的最优解。With the rapid development of communication technology,there are more and more researches on the signal integrity of high-speed circuit boards in the PCB industry,such as research in the direction of testing methods and manufacturing processes to ensure more accurate product loss data to ensure product quality.In the product engineering design stage,due to material selection,dielectric layer thickness design,line width/spacing design,signal line thickness and length design are different,and the loss performance of the manufactured circuit boards is also quite different.This article explores the above factors influencing the circuit board.The influence law of signal integrity is expected to obtain the optimal solution for signal integrity in engineering design.

关 键 词：高速电路板 信号完整性 插入损耗 工程设计 

分 类 号：TN41[电子电信—微电子学与固体电子学]