FBC分组密码算法的FPGA实现  

FPGA Implementation of FBC Block Cipher Algorithm

作　　者：肖超恩[1] 黄胜远 李秀滢[1] XIAO Chaoen;HUANG Shengyuan;LI Xiuying(Beijing Electronic Science and Technology Institute,Beijing 100070,P.R.China)

机构地区：[1]北京电子科技学院,北京市100070

出　　处：《北京电子科技学院学报》2020年第2期1-6,共6页Journal of Beijing Electronic Science And Technology Institute

基　　金：密码科学技术国家重点实验室开放课题(NO.MMKFKT201804);农产品质量安全追溯技术及应用国家工程实验室开放课题(AQT-2018-YB5);“中央高校基本科研业务费-328201914项目”资助

摘　　要：针对FBC分组密码算法软件实现效率低的问题,提出了一种FBC算法的FPGA(现场可编程门阵列,FPGA)硬件实现方案。首先,简要介绍了FBC算法工作原理。其次,将FPGA具有并行计算的特点与FBC算法结构相结合,采用模块化编程设计思想,使用有限状态机设计实现了FBC128-128加密算法。最后,在Xilinx Virtex5系列的XC5VFX100T芯片中运行结果表明,算法所使用的硬件资源为6795LUTs,在5ns时钟约束下加解密的吞吐率达到了522Mbps。Aiming at the problem of the low efficiency of FBC block cipher algorithm’s software implementation,an FPGA hardware implementation scheme of FBC algorithm is proposed.First,working principle of FBC algorithm is introduced briefly.Then,with combining the FPGA’s characteristic of parallel computing and the structure of FBC algorithm,FBC128-128 encryption algorithm is designed and implemented using a finite state machine with the idea of modular programming.Finally,experiment is performed with an XC5 VFX100 T chip in Xilinx Virtex5 series.Experiment result shows that the hardware resource used for the encryption operation is 7168 LUTs.With the clock of 5 ns,handling capacity of the encryption and decryption comes up to 522 Mbps.

关 键 词：FBC算法 FPGA 状态机设计 

分 类 号：TN791[电子电信—电路与系统] TN918.1