基于深度学习的布线违例预测方法  

Prediction of Detailed Routing Check Violations Using Deep Learning

作　　者：梁硕 李海华[1] LIANG Shuo;LI Haihua(School of Electronic Information and Electrical Engineering,Shanghai Jiao Tong University,Shanghai 200240,P.R.China)

机构地区：[1]上海交通大学电子信息与电气工程学院,上海200240

出　　处：《微电子学》2022年第6期1027-1032,共6页Microelectronics

摘　　要：在先进工艺下,VLSI布线产生设计规则违例(DRC)的原因十分复杂,这使得全局布线的拥塞度不再能准确地反映DRC的分布。针对这个问题,提出了一种基于深度学习的预测布线违例分布的方法。该方法只使用布局阶段的引脚、线网和宏模块等版图信息作为特征和CSMOTE算法平衡数据集,无需进行全局布线,然后使用卷积神经网络对数据进行训练,最后用训练模型预测M2 short和cut group space布线违例的分布。该方法在一个采用先进工艺的真实工业设计上进行了测试。结果显示,该方法预测M2 short的准确率为93.4%,F1值为0.78;预测cut group space的准确率为92.5%,F1值为0.78。The causes of VLSI design rule check violation(DRC)in advanced technology are very complex,which makes the congestion map of global routing can’t reflect the distribution of DRCs accurately.In this paper,a deep-learning based approach is proposed for predicting DRCs.Pin,net and macro information of placement rather than global routing were used as features.Then,these features were trained by a convolutional network after being processed by CSMOTE.Finally,M2 short and cut group space were predicted by this model.The method was tested in a real industrial design in advanced technology node.Experimental results show that the accuracy and F1 score on M2 short is 93.4%and 0.78 respectively,while 92.5%and 0.78 on cut group space.

关 键 词：布线违例 深度学习 电子设计自动化 布局 布线规则检查 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN47