一种可编程调频的L频段高性能电荷泵锁相环  

A High-Performance L-Band Charge-Pump PLL with Programmable Frequency Modulation

作　　者：王想军 刘博 王琳 邓智耀 张文飞 向菲 WANG Xiangjun;LIU Bo;WANG Lin;DENG Zhiyao;ZHANG Wenfei;XIANG Fei(Electrical Engineering College,Henan University of Science and Technology,Luoyang,Henan 471000,P.R.China)

机构地区：[1]河南科技大学电气工程学院,河南洛阳471000

出　　处：《微电子学》2022年第6期987-992,共6页Microelectronics

基　　金：国家自然科学基金资助项目(61704049);河南省科技厅重点科技攻关项目(192102210087)

摘　　要：基于SMIC 180 nm/1.8 V CMOS工艺,设计了一种高速、低功耗且具有输入选频和多水平调频输出范围的L频段电荷泵锁相环。输入端附加了四选一数据选择器,实现多频点信号的选频追踪,输出端设计了一种由新型P、S架构计数器构建的可编程双模分频器,实现高精度分频和连续位数的可编程输出。实验结果表明,锁相环最终锁定输出频率为1.1 GHz,从启动至稳频输出的锁定时间仅为1.5μs,整体电路功耗低至1.2 mW,同时可有效实现频率范围73 MHz至500 MHz的2~15位连续的可编程输出分频。完成锁相环电路的后端设计并提交流片,最终版图面积仅为0.027 mm^(2)。所提出的L频段锁相环可有效用于卫星降频信号接收、光信号调制和数字音频广播(T-DAB)等无线信号通信和处理系统。A high-speed,low-power-consumption L-band charge-pump phase-locked loop(CPPLL)with multi-input frequency selection and multilevel output frequency modulation range was designed in SMIC 180 nm/1.8 V CMOS technology.A 4-to-1 data selector was added at the input end to realize tracking and phase-locking of signal at multi-frequency point.At the output end,a programmable dual-modulus prescaler based on a novel P/S type counter was designed to realize high-precision frequency division and programmable continuous bit output.The experimental results show that,the locking time from startup to stabled 1.1 GHz output is 1.5μs and the power consumption can be lowered to 1.2 mW.In addition,the 2~15 bits continuous programmable frequency division can be realized with frequency tuning range of 73 MHz to 500 MHz.Finally,the layout design of the overall PLL circuit is implemented and the area is only 0.027 mm^(2),which had been transferred to SMIC for chip tapeout.The proposed L-band PLL can be effectively employed in wireless communication and RF signal processing systems,such as satellite down-frequency-receiving,optical signal modulation and digital audio broadcasting(T-DAB).

关 键 词：电荷泵锁相环 L频段 可编程调频 双模分频器 

分 类 号：TN432[电子电信—微电子学与固体电子学]