适用于高频开关芯片的快速瞬态响应LDO设计  

Design of a Fast Transient Response LDO for High Frequency Switching Chips

作　　者：毛帅 张杰[1] 明鑫[1,2] 张波[1] MAO Shuai;ZHANG Jie;MING Xin;ZHANG Bo(State Key Laboratory of Electronic Thin Films and Integrated Devices,UESTC,Chengdu 610054,P.R.China;Chongqing Institute of Microelectronics Industry Technology,UESTC,Chongqing401331,P.R.China)

机构地区：[1]电子科技大学电子薄膜与集成器件国家重点实验室,成都610054 [2]电子科技大学重庆微电子产业技术研究院,重庆401331

出　　处：《微电子学》2022年第6期974-980,共7页Microelectronics

基　　金：国家自然科学基金资助项目(61974019)

摘　　要：设计了一种片外大电容快速瞬态响应低压差线性稳压器。该LDO电路基于跨导线性结构设计,在输出级引入推挽结构,有效地减小过冲的幅值和恢复时间,提高了LDO的瞬态响应速度;利用浮动缓冲器驱动功率管,有效地提高了LDO的电流效率;采用动态零点补偿技术,保证了LDO在全负载范围内的环路稳定性。该LDO电路基于0.35μm BCD工艺设计与仿真验证。结果表明,在1.2 V~3 V输入电压范围,LDO的输出电压为1 V,静态电流约为50μA,可提供0~300 mA的负载。在上升下降沿为500 ns、幅度为300 mA、轻载持续时间为50μs的负载瞬态跳变下,过冲和下冲均小于20 mV。电路满足高频负载跳变的应用需求。An off-chip large capacitor fast transient response low dropout regulator was designed.The LDO introduced a push-pull structure in the output with the translinear circuit,which effectively reduced the amplitude and recovery time of the overshoot,and improved the transient response speed.The floating buffer was used to drive the power transistor,which effectively improved the LDO’s current efficiency.Dynamic zero compensation technology was adopted to ensure the loop stability of LDO in the all load conditions.The LDO was designed and simulated based on the 0.35μm BCD process.The results show the input voltage range of the LDO is in 1.2 V~3 V,the output voltage is 1 V,the quiescent current is about 50μA,and it can provide 0~3 mA load current.During load transients with 500 ns rising and falling edges,300 mA amplitude,50μs light load durations,the overshoot and undershoot are less than 20 mV,which meets the application requirements of high frequency load transition.

关 键 词：片外大电容LDO 快速瞬态响应 过冲恢复 高频负载跳变 

分 类 号：TN432[电子电信—微电子学与固体电子学]