一种高性能小数级联型锁相环电路  

A High-Performance Fractional-N Cascaded PLL Circuit

作　　者：滕海林 孟煦 王晓蕾[1] TENG Hailin;MENG Xu;WANG Xiaolei(IC Design Web-Cooperation Research Center of MOE,Institute of VLSI Design,Hefei Univ.of Technol.,Hefei 230601,P.R.China)

机构地区：[1]合肥工业大学微电子设计研究所,教育部IC设计网上合作研发中心,合肥230601

出　　处：《微电子学》2022年第6期967-973,共7页Microelectronics

基　　金：国家自然科学基金资助项目(61704043)

摘　　要：提出了一种低抖动、高频率分辨率、快速锁定的小数级联型锁相环。采用倍乘型延迟锁定环和基于和差调制器(DSM)的相位选择器实现小数倍频,并通过级联一个高带宽的整数型锁相环抬升频率且实现对DSM量化噪声的进一步滤除。基于TSMC 65 nm CMOS工艺,面积为0.27 mm^(2),输出频率为1.064~1.936 GHz。通过电路仿真输入100 MHz参考频率,PLL的1.872 GHz输出频率在300 ns以内完成锁定,1.2 V电源电压下整体功耗为8.6 mW。此时频率分辨率约1 kHz,1 kHz~100 MHz的积分范围内均方根抖动为1.32 ps。A fractional-N cascaded PLL with low jitter,fine frequency resolution,as well as fast-locking feature is proposed.An MDLL and a Delta-Sigma modulator(DSM)based on phase selector were adopted to achieve fractional frequency multiplication.Following that,a wideband integer-N PLL was employed to not only further multiply up the output frequency,but also filter away the residual DSM quantization noise.Implemented in TSMC 65 nm CMOS process,the overall PLL occupied a die area of 0.27 mm^(2)and covered the frequency range of 1.064 to 1.936 GHz.With the input frequency of 100 MHz,the PLL achieves locking within 300 ns when the output is 1.872 GHz,and the overall power consumption is 8.6 mW under 1.2 V supply voltage.The frequency resolution is about 1 kHz,and the RMS jitter is 1.32 ps in the integration range of 1 kHz to 100 MHz.

关 键 词：级联型锁相环 低抖动 高频率分辨率 快速锁定 

分 类 号：TN432[电子电信—微电子学与固体电子学]