一种14位100 MS/s的流水线模数转换器  

A 14 bit 100 MS/s Pipelined ADC

作　　者：吴唐政 王娜 谢亮 金湘亮 WU Tangzheng;WANG Na;XIE Liang;JIN Xiangliang(School of Physics and Optoelectronics,Xiangtan University,Xiangtan,Hunan 411105,P.R.China;Hunan Engineering Laboratory for Microelectronics,Optoelectronics and System on A Chip,Xiangtan,Hunan 411105,P.R.China;School of Physics and Electronics,Hunan Normal University,Changsha 410081,P.R.China)

机构地区：[1]湘潭大学物理与光电工程学院,湖南湘潭411105 [2]微光电与系统集成湖南省工程实验室,湖南湘潭411105 [3]湖南师范大学物理与电子科学学院,长沙410081

出　　处：《微电子学》2020年第1期6-10,共5页Microelectronics

基　　金：国家自然科学基金资助项目(61774129,61827812).

摘　　要：设计了一种14位100 MS/s的流水线模数转换器(ADC)。采样保持电路与第1级2.5位乘法数模转换器(MDAC1)共享运放,降低了功耗。提出了一种改进的跨导可变双输入开关运放,以满足采样保持和MDAC1对运放的不同要求,并消除记忆效应和级间串扰。ADC后级采用5级1.5位运放共享结构。基于0.18μm CMOS工艺,ADC核心面积为1.4 mm^2。后仿真结果表明,在1.8 V电源电压下,当采样速率为100 MS/s、输入信号频率为46 MHz时,ADC的信噪比(SNR)为82.6 dB,信噪失真比(SNDR)为78.7 dB,无杂散动态范围(SFDR)为84.1 dB,总谐波失真(THD)为-81.0 dB,有效位数(ENOB)达12.78位。ADC整体功耗为116 mW。A 14 bit 100 MS/s pipelined analog-to-digital converter(ADC)was designed.The opamp was shared by the sample-hold circuit and the 2.5 bit first stage multiplying digital-to-analog converter(MDAC1)to reduce power consumption.An improved dual-input switched opamp with variable transconductance was proposed to meet the different requirements of the sample-hold and MDAC1.Also,memory effect and crosstalk were eliminated by the improved switched opamp scheme.A five stage 1.5 bit opamp-sharing structure was adopted in the rest of pipeline stages.Based on a 0.18μm CMOS process,the proposed ADC core circuit occupied an area of 1.4 mm^2.The post simulation results showed that an SNR of 82.6 dB,an SNDR of 78.7 dB,an SFDR of 84.1 dB,a THD of-81.0 dB and an ENOB of 12.78 bit could be achieved with a sampling rate of 100 MS/s and an input signal frequency of 46 MHz.The overall power consumption of the ADC was 116 mW at 1.8 V power supply.

关 键 词：流水线模数转换器 运放共享 跨导可变 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN792