基于国产工艺的高速并串转换电路设计  

Design of a High-speed Serializer with a Domestic CMOS Process

作　　者：屈祥如 周威 牛晓阳[1] 赵承心 QU Xiangru;ZHOU Wei;NIU Xiaoyang;ZHAO Chengxin(Institute of Modern Physics,Chinese Academy of Sciences,Lanzhou 730000,China;School of Nuclear Science and Technology,University of Chinese Academy of Sciences,Beijing 100084,China)

机构地区：[1]中国科学院近代物理研究所,兰州730000 [2]中国科学院大学核科学与技术学院,北京100049

出　　处：《原子核物理评论》2022年第3期343-351,共9页Nuclear Physics Review

基　　金：国家自然科学基金青年项目(11875304,12005279,U2032209)

摘　　要：面向全国产化工艺的5 Gbps SerDes(Serializer/DESerializer,串化器/解串器)芯片的需求,设计了其中的20:1 Serializer(并串转换电路)。该并串转换电路基于国产GSMC 130 nm CMOS工艺设计,其内部电路结构设计采用了一级5:1模块和两级2:1模块级联方式,并由多相时钟发生器和分频器提供相应的时钟信号,将20路250 Mbps并行数据转换成1路5 Gbps的高速串行数据进行传输。在温度-40~100℃、全工艺角环境、电路工作电压在1.08~1.32 V的条件下,后仿真结果均显示该电路功能正确,能输出完整清晰的5 Gbps数据眼图,满足设计需求。其中在27℃、TT Corner(典型值工艺角)、1.2 V工作电压条件下仿真结果表明该并串转换电路整体总功耗为39.12 mW、总抖动为8.34 ps、输出电压满摆幅为800 mV。This paper designs a 20:1 Serializer for a 5 Gbps SerDes(Serializer/DESerializer)ASIC fabricated using China’s domestic GSMC 130 nm CMOS process.This Serializer converts the 20-bit 250 Mbps parallel data into 1-bit 5Gbps serial data.It consists of one stage of 5:1 conversion module and two stages of 2:1 conversion module.The clocks are provided by a multi-phase clock generator and a frequency divider.Post-simulations with all process corners,the temperature is from-40℃to 100℃and supply voltage is from 1.08 to 1.32 Volt,show this Serializer functions correctly and can generate a clear eye diagram at 5 Gbps,which fulfills the design requirements.Mainly,simulation with the typical process corner,the temperature at 27℃,and supply voltage at 1.2 Volt show that the total power dissipation is 39.12 mW,the total jitter is 8.34 ps,and the output voltage rail-to-rail is 800 mV.

关 键 词：并串转换电路 数据高速传输 国产CMOS工艺 SERDES 

分 类 号：TN402[电子电信—微电子学与固体电子学]