基于Pezaris算法的流水线阵列乘法器设计  

A Design of Pipeline Array Multiplier Based On Pezaris algorithm

作　　者：杨忠晔[1] 赵梅[1] 吴俊[1] 

机构地区：[1]苏州科技学院电子与信息工程系,江苏苏州215011

出　　处：《微计算机信息》2007年第23期303-304,276,共3页Control & Automation

基　　金：江苏省高新技术产业发展项目(JH03-018)

摘　　要：介绍了补码阵列乘法器的Pezaris算法。为提高运算速度,利用流水线技术进行改进,设计出流水线结构阵列乘法器,使用VHDL语言建模,在Quartus II集成开发环境下进行仿真和功能验证。The Pezaris algorithm of complement Array Multiplier has been introduced. For speeding up , it has been improved with the technique of pipeline. A N×N pipeline Array Multiplier has been designed with VHDL . The conclusion of Simulation and func- tion verification for it in the integration development environment of Quartus II has been given.

关 键 词：阵列乘法器 Pezaris算法 流水线 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]