适用于PCI-E接口的高速FIFO电路设计  

The Design of High-speed FIFO Circuit For The PCI-E Interface

作　　者：吕超[1] 刘伯安[1] 

机构地区：[1]清华大学微电子研究所,北京100084

出　　处：《微计算机信息》2008年第11期259-260,263,共3页Control & Automation

摘　　要：论文给出了一种适用于PCI-Express接口的用0.18μm标准CMOS工艺实现的基于动态存储器(DRAM)内核的高速大容量先入先出存储器(FIFO)电路及其版图设计。电路采用分块和Cell级连技术实现了高速、大容量的存储模块,外围电路用硬件描述语言(HDL)描述,存储模块版图用SKILL语言和ROD(Relative Object Design)编程实现,DRAM内核工作时钟频率达500M。In this paper, the first-in-first-out(FIFO) circuit design for the PCI-Express interface is proposed,which is based on the dynamic access memory (DRAM) core with the 0.18μm standard CMOS technology. The high-speed and high-capacity memory module is accomplished with the regional block , the periphery circuit is generated by the hardware description language(HDL) . The layout of the memory module is completed by the SKILL language and the ROD program. The clock frequency of the DRAM core is 500M.

关 键 词：先入先出 动态存储器 版图自动生成 

分 类 号：TN79[电子电信—电路与系统]