动态电路复杂性阶数显性约束条件的拓展  

The Development of Dominance Restraint Condition of the Order of Complexity of Dynamic Circuit

作　　者：刘童驎[1] 

机构地区：[1]山东大学电气工程学院,山东济南250061

出　　处：《电气电子教学学报》2007年第5期22-23,共2页Journal of Electrical and Electronic Education

摘　　要：动态电路复杂性阶数是电工理论的一个基本问题,降低复杂性阶数的原因分为显性约束和隐性约束。关于显性约束一般文献表述为C-us回路和L-is割集。本文论证了L-us回路和C-is割集同样可成为显性约束条件,并给出了实例验证。The order of complexity of dynamic circuit is a basic question of the electrician theory.The reason to reduce the complex order is divided into the dominant restraint and the recessive restraint.About the dominant restraint,common literature indicates to be C-us loop and Lis cut set.This article has proved that L-us loop and Cis cut set become dominant restraint condition similarly and gives some examples.

关 键 词：动态电路 复杂性阶数 显性约束 

分 类 号：TM13[电气工程—电工理论与新技术]