电荷泵PLL中PFD的设计  

Deign of PFD in CP-PLL Circuits

作　　者：王小伟[1] 吴金[1] 陆生礼[1] 黄晶生[1] 

机构地区：[1]东南大学IC学院,南京210096

出　　处：《电子器件》2007年第2期503-506,共4页Chinese Journal of Electron Devices

摘　　要：在电荷泵锁相环CP-PLL原理分析基础上,对其重要的组成模块鉴频鉴相器(PFD)进行了详细的理论分析和电路设计.在VCO的动态范围内,可实现任意频率误差下的快速频率跟踪,并最终实现零相位锁定.和一般的鉴相器比较,PFD工作在大的范围(-2π～+2π),实现零相位误差.电路通过了基于上华0.5μmCMOS工艺的HSPICE模拟仿真验证,得到在5V电源电压和27MHz/s的参考频率下,PFD的增益Kpd为5/4πV/rad.Based on the analysis of principle of charge-pump Phase locked Loop,the PFD,which is one of the critical building blocks in CP-PLL,is comprehensively analyzed in theory and designed.The circuit can quickly track frequency under any frequency errors in the dynamic range of VCO,and finally,achieve phase locked.Compared to general PD,it has a much larger phase range(-2π～+2π)of operation and zero offset of phase.The simulation results which based on the CSMC 0.5 μm mixed signal CMOS technology by HSPICE can del...

关 键 词：锁相环 鉴频鉴相器 频率/相位锁定 电荷泵 

分 类 号：TN763[电子电信—电路与系统]