SoC设计中的低功耗策略  

Low Power Strategy in SoC Design

作　　者：张富彬[1] HO Ching-Yen 彭思龙[1] 

机构地区：[1]中国科学院自动化研究所国家专用集成电路设计工程研究中心 [2]Synopsys Inc.Mountain View CA 94043

出　　处：《电子器件》2007年第2期633-637,共5页Chinese Journal of Electron Devices

摘　　要：低功耗设计已经成为片上系统(SoC)设计的主题.当今的设计已经从过去的性能、面积二维目标转变为性能、面积和功耗的三维目标.本文深入探讨了片上系统设计中的低功耗设计策略,在晶体管和逻辑门级、寄存器传输级和系统结构级各设计抽象层次上阐述了低功耗设计所面临的问题,并给出了各级的低功耗优化策略.Low power has emerged as a principal theme in today's SoC design.Power has became as important as performance and area in SoC design.This paper presents an in-depth discussion of low power design strategies in SoC design and describes the many issues facing designers at transistor and gate,RTL and system levels of design abstraction.Finally it provides all kings of low power design strategies at every abstraction levels.

关 键 词：低功耗 片上系统 静态功耗 动态功耗 动态功耗管理 

分 类 号：TN47[电子电信—微电子学与固体电子学]