高速自适应DLMS算法及其硬件实现  

High speed adaptive DLMS algorithm and its hardware implementation

作　　者：陈文博[1] 耿相铭[1] 马伟敏[1] 

机构地区：[1]上海交通大学电子工程系,上海200240

出　　处：《信息技术》2007年第10期59-62,共4页Information Technology

摘　　要：针对LMS算法在硬件实现时的"缺陷",提出了一种适合高速实时处理的改进型DLMS算法。算法通过分离自适应处理中的滤波和权系数更新两个过程,使其实现并行运算;并且可以直接映射到具体的硬件中。作为示例,依据此改进DLMS算法设计了一种折叠型自适应滤波器,并用Xilinx Virtex-4 FPGA实现此设计,给出具体的验证结果。Based on the limitation of designing hardware with LMS algorithm,an improved DLMS algorithm which is suitable for high speed real time signal processing is put forward in this paper.This algorithm separates the filter module and the weight coefficient adaptation module,which are operated in parallel,and can be easily realized with specific hardware like ASIC and FPGA.As an example,a folded improved DLMS adaptive filter was designed and realized with Xilinx Virtex-4 FPGA,some true results were given too.

关 键 词：DLMS LMS 高速实时处理 折叠结构 FPGA 

分 类 号：TN911.7[电子电信—通信与信息系统]