基于CSL架构的低功耗CMOS环型振荡器的设计  

A Low-power CMOS Ring-Based Oscillator Using Current Steering Logic Structure

作　　者：周海峰[1] 韩雁[1] 

机构地区：[1]浙江大学微电子与光电子研究所,浙江杭州310027

出　　处：《杭州电子科技大学学报（自然科学版）》2007年第5期34-38,共5页Journal of Hangzhou Dianzi University：Natural Sciences

摘　　要：该文设计了一种基于电流控制逻辑架构的1.8GHz低功耗环型压控振荡器,分析了p型电流控制逻辑,并作为环振的延迟单元。该环型振荡器采用SMIC 0.18μm CMOS工艺实现。在1.8V电压下,具有大于1GHz的调谐范围,相位噪声为-96.4dBc/Hz@3MHz,功耗是1.40mW。与其他已报道的类似结构相比,该设计具有更好的性能。A completely integrated 1.8GHz low-power ring-based voltage-controlled oscillator(VCO) is designed in SMIC 0.18μm CMOS process by using p-type current steering logic(CSL) structure as the delay cell.With single 1.8V supply,it has a tuning range of 1GHz and a phase noise of-96.4dBc/Hz at 3MHz offset from center frequency through out the tuning range.The total power consumption is 1.40mW.Comparison shows that this design has better performance than previously published similar results.

关 键 词：低功耗 电流控制逻辑 压控振荡器 

分 类 号：TN752[电子电信—电路与系统]