CMOS模拟集成电路匹配技术及其应用  

Matching Technique of CMOS Analog IC Design and Its Application

作　　者：吴大勇[1] 马琪[1] 蒋平[1] 

机构地区：[1]杭州电子科技大学微电子CAD研究所,浙江杭州310018

出　　处：《杭州电子科技大学学报（自然科学版）》2007年第6期13-16,共4页Journal of Hangzhou Dianzi University：Natural Sciences

基　　金：浙江省科技厅重大科技计划(Z10052)

摘　　要：集成电路工艺变化引起失配,而模拟集成电路匹配特性影响电路的性能,电路达到适当的匹配已成为模拟电路设计的一个重要设计目标。该文阐述了失配的机理,分析了失配引起电路共模抑制比降低、失调和偶次失真等影响,在此基础上研究了消除一阶工艺梯度偏差的匹配版图技术,并针对一运放电路分析了匹配技术在运放版图设计中的应用。Process variation produces mismatch,matching characteristics of analog IC have a great effect on circuit performance.And achieving moderate matching has become the target of analog IC design.This paper analyzes the mechanisms that lead to devices mismatch and its effect upon the circuit performance including reducing CMRR,producing offsetting and even order distortion,describes some layout techniques for minimum mismatch that can eliminate the first order of process gradients,and show the application of these technique on the layout design of an operational amplifier.

关 键 词：模拟集成电路 版图 匹配 运放 

分 类 号：TN402[电子电信—微电子学与固体电子学]