微型加速度测试仪的ASIC实现  

ASIC implementation for tiny acceleration recording system

作　　者：靳鸿[1] 祖静[1] 张志杰[1] 

机构地区：[1]中北大学电子测试技术国家重点实验室,太原030051

出　　处：《仪器仪表学报》2006年第z2期1530-1531,共2页Chinese Journal of Scientific Instrument

摘　　要：本文设计了一种微型加速度记录仪用数字ASIC,它采用可编程设计技术,达到了小体积、低功耗及多用途设计目标。样片采用0．8μm工艺制造,封装尺寸为9×9mm。实际测试表明,它能够满足恶劣环境下的加速度采集要求。The paper introduces an ASIC for Tiny accelerate recording system(TARS) . The field reprogrammable technology has been used in the ASIC's design,and it has achieved the goal of the small volume, the low power loss and the multipurpose design. The ASIC was produced in 0. 8μm CMOS process and the package size is 9×9mm. The experiment results show that the chip works well and can be used in different purpose TARS.

关 键 词：加速度 微型 存储测试 专用集成电路(ASIC) 可编程 

分 类 号：TH7-55[机械工程—仪器科学与技术]