变组相连缓存结构的设计和故障注入验证分析  

Exploring Good Cache Architecture

作　　者：马捷中[1] 郭阳明[1] 曾宪炼[1] 何世强[1] 

机构地区：[1]西北工业大学计算机学院,陕西西安710072

出　　处：《西北工业大学学报》2009年第6期863-866,共4页Journal of Northwestern Polytechnical University

基　　金：陕西省自然科学基金(SJ08F20);航空科学基金(2008ZD53035)资助

摘　　要：缓存是CPU与内存之间解决速度匹配问题的中介,文章研究了一种变组相连的缓存结构和缓存容错机制,通过基于软件的故障注入试验,结果表明该结构硬件成本小于全相连,但缓存命中率与全相连相似;故障探测率高于全相连,接近组相连,是综合性能较优的缓存结构。We aim to explore a cache architecture whose hit ratio is almost as high as the available best but whose power consumption is low and whose hardware is reduced to a minimum.Section 1 of the full paper discusses,with the help of Figs.1,2 and 3,the design of the cache architecture we explored.Section 2 designs the fault tolerance of cache architecture.Finally we purposefully perform fault injection to test the reliability of the cache architecture.The test results,given in Table 2,show preliminarily that the ...

关 键 词：缓存结构 变组相连 命中率 故障注入 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]