地震数据采集中基于FPGA的多DDR SDRAM控制器设计  

A design of multiple DDR SDRAM controllers based on FPGA in a seismic data acquisition system

作　　者：马灵[1] 杨俊峰[1] 宋克柱[1] 王砚方[1] 

机构地区：[1]中国科学技术大学近代物理系,安徽合肥230026

出　　处：《中国科学技术大学学报》2010年第9期939-945,共7页JUSTC

基　　金：中国高技术研究发展(863)计划(2006AA09A10202)资助

摘　　要：实现高速大容量数据的无死时间乒乓存储是地震数据采集系统的一项关键技术,本设计采用在一片FPGA中,通过共享同一个PLL和DLL来实现2个DDR SDRAM控制器,应用于海上高精度地震拖缆采集与记录系统中光纤控制接口板上,完成对水下地震采集数据的接收、乒乓缓存、数据拼接及时序转道序功能.最终系统仿真和测试结果表明,该控制器能够在133MHz频率上稳定运行,达到了预期的设计目标.High-speed and high-capacity data ping-pong storage without dead time is a key technology in seismic data acquisition systems.A design was proposed that realizes two DDR SDRAM controllers by sharing the same PLL and DLL in an FPGA and was applied in the fiber connection interface board(FCI)in high-precision marine seismic data acquisition and recording systems.The FCI is responsible for seismic data reception,data ping-pong storage,data convertion from time sequence into channel sequence,etc.Final system simulation and test results showed that the controllers can be operated stably at the frequency of 133 MHz,achieving the expected goal of the design.

关 键 词：FPGA DDR SDRAM控制器 乒乓存储 SignalTapⅡ逻辑分析仪 

分 类 号：TP274.2[自动化与计算机技术—检测技术与自动化装置]