AN EFFICIENT IMPLEMENTATION ARCHITECTURE FOR WIDE-BAND DIGITAL DOWNCONVERSION  

作　　者：Gao Zhicheng Xiao Xianci (University of Electronic Science and Technology of China, Chengdu 610054) 

出　　处：《Journal of Electronics(China)》2001年第1期38-45,共8页电子科学学刊（英文版）

摘　　要：The wide-band digital receiving systems require digital downconversion(DDC) with high data rate and short tuning time in order to intercept the narrow-band signals within broad tuning bandwidth. But these requirements can not be met by the commercial DDC. In this paper an efficient implementation architecture is presented. It combines the flexibility of DFT tuning with the efficiency of the polyphase filter bank decomposition. By first decimating the data prior to filtering and mixing, this architecture gives a better solution to the mismatch between the lower hardware speed and high data rate. The computer simulations show the feasibility of this processing architecture.The wide-band digital receiving systems require digital downconversion(DDC) with high data rate and short tuning time in order to intercept the narrow-band signals within broad tuning bandwidth. But these requirements can not be met by the commercial DDC. In this paper an efficient implementation architecture is presented. It combines the flexibility of DFT tuning with the efficiency of the polyphase filter bank decomposition. By first decimating the data prior to filtering and mixing, this architecture gives a better solution to the mismatch between the lower hardware speed and high data rate. The computer simulations show the feasibility of this processing architecture.

关 键 词：DIGITAL DOWNCONVERSION WIDE-BAND DIGITAL receiving POLYPHASE FILTER 

分 类 号：TN[电子电信]