The DPGA for Conbining the Superscalar and Multithreaded Processors Principal  

作　　者：Abdelkadel Chaib, Hu Mingzeng (Department of Computer Science and Technology, Harbin Institute of Technology, Harbin 150001 P.R.China) 

出　　处：《High Technology Letters》2001年第1期79-85,共7页高技术通讯（英文版）

摘　　要：The performance of scalable shared-memory multiprocessors suffers from three types of latency; memory latency, the latency caused by inter-process synchronization ,and the latency caused by instructions that take multiple cycles to produce results To tolerate these three types of latencies, The following techniques was proposed to couple: coarse-grained multithreading, the superscalar processor and a reconfigurable device, namely the overlapping long latency operations of one thread of computation with the execution of other threads The superscalar processor principle is used to tolerate instruction latency by issuing several instructions simultaneously The DPGA is coupled with this processor in order to improve the context-switchingThe performance of scalable shared-memory multiprocessors suffers from three types of latency; memory latency, the latency caused by inter-process synchronization ,and the latency caused by instructions that take multiple cycles to produce results To tolerate these three types of latencies, The following techniques was proposed to couple: coarse-grained multithreading, the superscalar processor and a reconfigurable device, namely the overlapping long latency operations of one thread of computation with the execution of other threads The superscalar processor principle is used to tolerate instruction latency by issuing several instructions simultaneously The DPGA is coupled with this processor in order to improve the context-switching overhead

关 键 词：DPGA Context switching Functional and control conflicts Data dependencies WAW RAW WAR hazards Tomasolo’s algorithm 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]