一种低噪声高PSRR的LDO线性稳压器  

Design of LDO voltage regulator with low noise and high PSRR

作　　者：邹静[1] 杨维明[1] 蒋师[1] 刘雪[1] 

机构地区：[1]湖北大学物理学与电子技术学院,湖北武汉430062

出　　处：《湖北大学学报（自然科学版）》2012年第3期360-364,372,共6页Journal of Hubei University：Natural Science

基　　金：湖北省教学研究项目(2009164)资助

摘　　要：介绍了LDO线性稳压器的系统组成原理,分析了系统的电源电压抑制比(PSRR)以及噪声与电路结构的关系,在此基础上,对LDO的核心电路模块进行了设计,并基于0.5μm标准CMOS工艺,运用Cadence平台进行了模拟仿真和验证.测试结果表明:该LDO的PSRR最低约为-45dB@1 MHz,最高约为-75dB@217Hz;输出电压噪声在10Hz频率以下约为0.78μV(P-P),在10Hz至100kHz频率范围内约为0.1μV(RMS),能满足低噪声和高PSRR应用的要求.After the composition principle of the LDO voltage regulator was introduced,the relationship between the circuit structure and the power supply noise rejection ratio(PSRR)or the noise performances were analyzed.Basing on this,the detail design of the key circuit units of the LDO was presented.Then the main performances of the LDO were simulated and verified by using 0.5μm standard CMOS technology and Cadence software tool.The test results indicate that the PSRR of the sample is from-45dB@1 MHz to-75dB@217 Hz.The output voltage noise is about 0.78μV(P-P)at 10 Hz below,and 0.1 μV(RMS)from 10 Hz to 100kHz.It can meet the needs of low power consumption,low noise,and high PSRR application.

关 键 词：线性稳压器 低噪声 电源电压抑制比 

分 类 号：TN431.1[电子电信—微电子学与固体电子学]