一种基于混合模式时钟管理器的时钟频率动态重置改进算法  

An improved algorithm for clock frequency dynamic reconfiguration based on mixed-mode clock manager

作　　者：蒋雪凝[1] 徐新民[1] Oliver Faust 

机构地区：[1]浙江大学信息与电子工程学系,浙江杭州310027 [2]义安理工学院电子与计算机工程学系,新加坡599489

出　　处：《浙江大学学报（理学版）》2012年第6期643-647,共5页Journal of Zhejiang University（Science Edition）

摘　　要：针对现有混合模式时钟管理器(Mixed-Mode Clock Manager,MMCM)动态重置算法占用大量ROM空间、与用户交互性不强的问题,提出一种MMCM动态重置改进型算法(IDRA).MMCM有7个输出端,可为不同电路模块提供时钟信号,直接输入MMCM输出端口序号和频率值即可改变相应端口的输出时钟频率.动态重置端口(Dynamic reconfiguration port,DRP)与加强型MMCM原型连接,采用状态机来驱动DRP,顺序实现读取输出端口寄存器地址、选择改变输出时钟频率或相移、读取分频值、使能端口寄存器读写等功能.最后,给出0号输出端口时钟频率由100MHz降为50MHz的仿真波形,此频率可变范围为4.69～700MHz.An improved MMCM dynamic reconfiguration algorithm(IDRA) is proposed to solve problems of taking up a lot of ROM and weak interaction with users of the existing algorithm.MMCM has seven outputs which provide clock signals for different circuit modules.It can change the output clock frequency of corresponding port by directly entering the port number and frequency data.IDRA is composed by DRP connecting to an advanced MMCM primi-tive,and DRP is driven by a state machine.It reads addresses of output registers,selects to change frequency or phase shift,reads divisor and enables reading and writing functions of port registers.Conversion range of MMCM outputs clock frequency is from 4.69 MHz to 700 MHz.The simulation of clock frequency changed from 100 MHz to 50 MHz of No.0 out put port is showed.

关 键 词：混合模式时钟管理器 时钟频率 动态重置端口 状态机 

分 类 号：TN492[电子电信—微电子学与固体电子学] TN79+1