逻辑内建自测移相器的设计与优化  

Design of Phase Shifter for Logic BIST

作　　者：梁骏[1] 胡海波[1] 张明[1] 

机构地区：[1]浙江大学信电系,浙江杭州310027

出　　处：《电路与系统学报》2004年第4期103-106,137,共5页Journal of Circuits and Systems

摘　　要：逻辑内建自测(Logic BIST)测试结构是今后系统芯片(SOC)设计中芯片测试的发展方向。由于LFSR(线性反馈移位寄存器)生成的伪随机序列的高相关性导致故障覆盖率达不到要求,采用移相器可以降低随机序列的空间相关性,提高Logic BIST的故障覆盖率。本文分析了移相器的数学理论并提出了移相器设计与优化算法。该算法可以得到最小时延与面积代价下的高效移相器。Logic Build In Self Test (BIST) will be widely used as an efficient Design For Test (DFT) tool in system on chip(SOC) technology. The high correlation of pseudo-random sequences produced by Linear Feedback Shift Register (LFSR) affects test coverage. Implementing phase shifter can reduce the correlation, which will improve test coverage of BIST. This paper introduces the mathematical theory of phase shifter and develops a new algorithm for design phase shifters with minimum cost of delay and speed.

关 键 词：LFSR BIST 移相器 SOC DFT(可测性设计) 

分 类 号：TN401[电子电信—微电子学与固体电子学]