用于GPS接收机的CMOS RSSI电路的设计  

CMOS RSSI Design for GPS Receiver

作　　者：孙杨[1] 张晓林[1] 夏温博[1] 

机构地区：[1]北京航空航天大学电子信息工程学院,北京100191

出　　处：《遥测遥控》2010年第5期35-38,共4页Journal of Telemetry,Tracking and Command

基　　金：国防科工委民用航天专项资助项目

摘　　要：基于GPS接收机射频前端芯片组,设计一种采用SMIC 0.18μm CMOS工艺的限幅放大器和RSSI电路。电路采用差分结构,减小了电路中器件不匹配的影响。限幅放大器单元采用折叠共源共栅式折叠二极管负载结构,这种结构适合低电源电压工作,同时具有良好的工艺稳定性。直流偏移消除电路采用交叉连接的源极耦合对结构。仿真结果显示,在1.8V的电源电压条件下,限幅放大器增益70dB,带宽100MHz,RSSI的动态范围大于55 dB,线性误差小于1dB,总体功耗约为3.7 mW。This paper describes low-power CMOS circuit design techniques for a limiting amplifier and received signal strength indicator(RSSI) circuits for the GPS receiver.The circuits in limiting amplifier and RSSI are all preudo differential to minimize the requirement of the supply voltage and be prepared against the device mismatch.A folded diode load and folded cascade structure gain cell is introduced for each gain cell of the amplifier.The architecture of the offset subtracter is a cross-connected source-coupled pair.Based on the SMIC 0.18μm CMOS technique with a 1.8V supply,the gain of the limiting amplifier is 70dB,and the RSSI provides 55dB of log-linear range with less than 1dB error due to process variation.The overall power consumption is 3.7mW.

关 键 词：CMOS模拟集成电路 限幅放大器 RSSI GPS接收机 

分 类 号：TN967.1[电子电信—信号与信息处理]