用于高速网络安全协处理器的抗功耗攻击AES算法引擎设计  

Power analysis resistant AES crypto engine design for a network security co-processor

作　　者：乌力吉[1] 季莹婕 张向民[1] 李翔宇[1] 杨永生[2] 

机构地区：[1]清华大学微电子学研究所信息科学与技术国家实验室,北京100084 [2]四川大学电子信息学院,成都610065

出　　处：《清华大学学报（自然科学版）》2009年第S2期2097-2102,共6页Journal of Tsinghua University(Science and Technology)

摘　　要：为提高密码算法芯片抵抗侧信道攻击,尤其是功耗攻击技术的能力,针对一款用于高速网络安全协处理器中的AES(高级加密标准)算法引擎,采用了软件级数据掩模方法进行了抗功耗攻击的电路设计。该设计中的AES算法引擎的原始模块是一种加解密共用S-box的结构,采用2种完全不同的方法实现了抗功耗攻击电路:一种采用SRAM(static random access memory)方式来实现数据掩盖,另一种基于硬件复制方式。通过产生随机功耗或虚假功耗以掩盖实际功耗与加解密数据运算之间的关系。使用功耗仿真软件PrimePower进行仿真的结果表明,未加保护的电路在1 000条功耗曲线内就可以被攻破,采用了本设计的电路可以抵抗10 000条以上的功耗曲线,可见AES算法引擎的安全性有显著的提高。经FPGA(field programmable gate array)验证,证明本文提出的2种设计均是可行的。A low power masking technique is used to promote the power attack resistant of the AES(advanced encryption standard) crypto engine in high performance network security co-processors to achieve higher security against the side-channel attack technique,especially the power analysis attack.The data masking novel circuit design utilizing SRAM(static random access memory) with replication in other modules.The design uses data masking to generate random power to disguise the genuine power related to the secret data being analyzed.The attacker will then not be able to find the relationship between the power and the data.The power simulator PrimePower is used to collect power curves at each round when ciphering.Comparison shows that the original crypto engine can be successfully attacked within 1000 different power curves,while the masked crypto engines in the design can resist over 10000 curves.Thus,the security of the AES crypto engine is greatly improved by the design.Furthermore,the design is verified to be feasible by FPGA(field programmable gate array).

关 键 词：微电子学 功耗攻击 AES(高级加密标准) 掩模 侧信道 

分 类 号：TP393.05[自动化与计算机技术—计算机应用技术]