基于查表法的多项式内插器的实现  

Implementation of Polynomial Interpolation Based on Look-up Table

作　　者：杨再初 潘长勇[1,2,3] 

机构地区：[1]清华大学电子工程系 [2]清华信息科学与技术国家实验室 [3]微波与数字通信技术国家重点实验室,北京100084

出　　处：《电视技术》2009年第S2期139-141,共3页Video Engineering

基　　金：国家"863"计划项目(2007AA01Z2B6);教育部新世纪优秀人才支持计划项目

摘　　要：提出了一种基于查表的多项式内插器结构,解决了多路并行内插占用大量乘法器资源的问题。首先证明了内插多项式系数存在一种对称关系,然后利用此关系设计了基于查表法的多项式内插器,并在FPGA上实现。实现结果表明:本方法结构简单,占用乘法器资源少,其复杂度与内查多项式的阶数无关,不足之处是需要占用很多的存储器资源。A novel architecture based on look -up table is proposed in this paper,which greatly reduces the number of multipliers that a parallel polynomial interpolator consumes.First of all,a character of symmetry in the coefficients of polynomial interpolator is proved.And then,a look-up table is designed according to the symmetry property.Finally,an example interpolator with this structure is implemented in FPGA.Implementation results show that the new method greatly reduces the number of multipliers by using the RAM in FPGA compared with Farrow structure.In parallel interpolation structure the new method has more advantages due to its simple structure.

关 键 词：多项式内插 并行内插 查表法 

分 类 号：TN791[电子电信—电路与系统]