ON SHORTENING TEST SEQUENCE LENGTH FOR SIGNATURE ANALYZER  

作　　者：丁瑾 胡健栋 

机构地区：[1]Beijing University of Posts and Telecommunications, Beijing 100088

出　　处：《Journal of Electronics(China)》1995年第2期151-159,共9页电子科学学刊（英文版）

基　　金：Supported by the State Education Commission Fund for Returned Man

摘　　要：Based on the built-in self-test for logic circuit, a new approach is proposed to reduce pseudorandom test length. After finding worst faults in the circuit and creating their circuit models the output signals of these models will be compressed by linear feedback shift register. The test length for the worst faults can be obtained by analyzing compressed signature . Finally, using the relation between input probability and test length, we propose a new algorithm to shorten the test sequence length. So the optimum input probability and the shortest test length can be received.Based on the built-in self-test for logic circuit, a new approach is proposed to reduce pseudorandom test length. After finding worst faults in the circuit and creating their circuit models the output signals of these models will be compressed by linear feedback shift register. The test length for the worst faults can be obtained by analyzing compressed signature . Finally, using the relation between input probability and test length, we propose a new algorithm to shorten the test sequence length. So the optimum input probability and the shortest test length can be received.

关 键 词：BUILT-IN SELF-TEST Worst FAULT SIGNATURE analysis Probability optimization 

分 类 号：TN702[电子电信—电路与系统]