数据综合仪码型发生模块设计  

The design of pattern generator module in a data synthesized analyzer

作　　者：韩熙利[1] 杨万渝[1] 

机构地区：[1]电子科技大学自动化工程学院,成都611731

出　　处：《仪器仪表学报》2013年第S1期72-77,共6页Chinese Journal of Scientific Instrument

摘　　要：本文给出了一种兼具逻辑分析仪和码型发生器功能的综合型数据域仪器的实现方案,重点阐述了码型发生器模块的设计。该码型发生器通过FPGA实现PCI接口功能,具有250M的数据发生率和64位输出通道,板载动态存储器实现每通道64M位的存储深度。可提供多种常见通信编码输出,也可通过列表和波形方式预先编辑码型数据块。配合不同的驱动器可提供TTL、LVTTL、CMOS、LVDS、PECL、LVPECL、ECL等多种电平输出。This paper presents a project of data synthesized analyzer which integrated by a logic analyzer and a pattern generator, and described the design of pattern generator in detail which connected to PCI via interface circuit designed in FPGA. The pattern generator's Clock output rate is 300 MHz maximum, and it has 64 output channels which every one has 64M depths realized by dynamic storage onboard. Many types of code message are provided as well as users can conveniently enter data blocks in list editor or waveform editor. Equipped with various drivers users can get TTL、LVTTL、CMOS、LVDS、PECL、LVPECL、ECL outputs.

关 键 词：数据域仪器 码型发生器 PCI接口 动态存储器 编码 

分 类 号：TM935[电气工程—电力电子与电力传动]