采用DWA技术的多位Σ-Δ调制器的设计  

Multibit Σ-Δ Modulator with Data Weighted Averaging Technique

作　　者：徐思龙[1,2] 李宗伟[1,2] 丛宁[1,2] 

机构地区：[1]中国科学院地质与地球物理研究所,北京100029 [2]中国科学院大学,北京100049

出　　处：《微电子学与计算机》2015年第1期140-145,共6页Microelectronics & Computer

摘　　要：设计一个内部采用2位量化器的二阶单环Σ-Δ调制器.为解决反馈回路中多位DAC元件失配导致的信号谐波失真问题,该调制器采用了数据加权平均(Data Weighted Averaging,DWA)技术来提高多位DAC的线性度.Σ-Δ调制器信号带宽为50kHz,过采样率(OSR)为64,采用MXIC公司的0.35μm混合信号CMOS工艺实现,工作电压为12V.后仿真结果显示,在电容随机失配5%的情况下,该调制器可以达到55.8dB的信噪比(SNR)和60.4dB的无杂散动态范围(SFDR).打开DWA电路比关闭DWA电路的情况下,SNR和SFDR分别提高8dB和13dB.整个调制器功耗为48mW,面积仅为0.6mm2.A second order single-loop multibitΣ-Δmodulator was designed with a 2-bits quantizer inside,and it was used for digital audio application.The modulator used multibit quantization and the data weighted averaging(DWA)technique was adopted to reduce the nonlinearity introduced by multibit quantizer.The Σ-Δ modulator was fabricated in a MXIC's 0.35μm mixed-signal CMOS process with 12 V supply voltage,and the input signal bandwidth was 50 kHz at oversampling rate(OSR)of 64.The post-simulation showed that the modulator can achieve 55.8dB SNR and 60.4dB SFDR with 5%capacitor mismatch.Contrast to close the DWA circuit,open the DWA circuit can increase 8dB SNR and 13 dB SFDR.The whole modulator dissipates 48 mW,and the area of the modulator is just 0.6mm2.

关 键 词：Σ-Δ调制器 开关电容积分器 多位量化器 DWA 

分 类 号：TN761[电子电信—电路与系统]