一种基于DCO的可配置数字频率合成器  

A DCO-Based Configurable Digital Frequency Synthesizer

作　　者：文治平[1] 王浩弛 陈雷[1] 李学武[1] 张彦龙[1] 

机构地区：[1]北京微电子技术研究所,北京100076

出　　处：《微电子学与计算机》2015年第4期125-128,133,共5页Microelectronics & Computer

摘　　要：首先设计了一种基于MDLL的数控振荡器(DCO),进而实现了一种基于DCO的全数字可配置的数字频率合成器(DFS),输出时钟频率等于参考时钟频率乘以M除以D,实现了类似于MDLL的抖动特性.频率合成器提供一个可配置的倍频因子M和一个分频因子D,其范围为2~32和1~32,用户可以通过对M和D的配置,实现任意倍数的频率合成.所设计的DFS采用TSMC的0.13mm标准CMOS工艺实现,版图面积为480μm×120μm.DFS的输出频率范围为15~400 MHz,输入频率范围为1~270 MHz.输出频率为270 MHz时实测的相位噪声为-110.01dBc/Hz@1 MHz.This paper presents a digitally controlled oscillator(DCO)based on a multiplying delay locked loop(MDLL),and a DCO-based configurable digital frequency synthesizer(DFS)is implemented.The output clock frequency is equal to the reference clock frequency multiplied by M divided by D.The multiplication ratio M and division ratio Dcan be programmed from 2to 32,and 1to 32,respectively.The frequency synthesizer achieves similar jitter performance as conventional MDLL.The DFS is implemented in TSMC 0.13-μm CMOS technology,with a layout area of 480μm×120μm.The frequency range of the input and output clock are 1~ 270 MHz and 15~ 400 MHz,respectively.The measured phase noise is-110.01dBc/Hz@1MHz,when the output clock frequency is 270 MHz.

关 键 词：数控振荡器(DCO) 可配置 数字频率合成器(DFS) 

分 类 号：TN74[电子电信—电路与系统]