基于FPGA的三操作数前导1预测算法的设计与性能分析  

Design and Performance Analysis of a Three-Operand Leading-one Prediction Algorithm Based on FPGA

作　　者：罗淑贞[1] 富坤[1] 高艳[1] 孙豪赛 耿跃华[3] 

机构地区：[1]河北工业大学计算机科学与软件学院,天津300401 [2]天津理工大学自动化学院,天津300384 [3]河北工业大学电气工程学院,天津300130

出　　处：《微电子学与计算机》2015年第5期41-45,50,共6页Microelectronics & Computer

基　　金：国家自然科学基金(31100711);河北省高等学校科学技术研究青年基金(20111122);河北省交通运输厅科学技术项目计划(Y2011087)

摘　　要：针对传统算法的局限,在FPGA平台上设计了直接处理三操作数的前导1预测算法的完整实现方案,可以有效缩短关键路径延时和功耗.重点设计出了三操作数的编码树结构,并依据预编码规则,在FPGA硬件验证平台上对系统结构合理模块化,且采用硬件描述语言VerilogHDL对部分功能进行编程,优化了设计过程,仿真结果表明,设计完成的算法结构较传统算法在关键路径延时上减少36.15%,功耗降低39.20%.In this paper,a method is adopted to deal directly with three-operand on FPGA platform and three operands complete prediction algorithm implementation is designed.This method can reduce the critical path delay and power consumption.The article focused on the design of three-operands encoding tree structure,and based on the pre-encoding rules on FPGA hardware verification platform,reasonable modular for system architecture,using hardware description language VerilogHDL to program some function module to optimize the design process and last the results are analyzed and verified.Compared with the design using the traditional algorithm,the one using the proposed algorithm can reduce the delay of the critical path by 36.15%,and reduce power consumption by 39.20%.

关 键 词：前导1预测算法 三操作数 FPGA VERILOGHDL 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]