基于核级冗余的可重配置多核系统硬件模块设计与实现  

Design and Implementation of Reconfigurable Hardware Module in Multi-core System Based on Core-level Redundancy

作　　者：路禹[1] 付方发[1] 王进祥[1] 

机构地区：[1]哈尔滨工业大学微电子中心,黑龙江哈尔滨150001

出　　处：《微电子学与计算机》2015年第6期67-72,共6页Microelectronics & Computer

摘　　要：在核级冗余的思想下,基于M5模拟器,设计实现了可重配置的新型片上网络硬件模块.该模块主要特点在于每个网络接口物理连接了四个路由器,同时每个路由器也与四个网络接口相连,构建了交叉互连的网络结构,支持在动态过程中重构通信网络结构,并保持原有的拓扑结构不变.整个硬件模块采用C++语言进行系统级建模,并在最后采用MPI并行编程,进行了网络重构的系统级验证,确保了该模块功能的正确性.A new reconfigurable hardware module of NoC is designed in this paper,which is based on MS simulater,according to the core level redundang.The main characteristic of the module is that each of the Network Interfaces(NI)physically connects to four routers,and each of the routers physically connects to four network interfaces to build cross interconnection network structure.The structure supports to reconstruct communication network,and the topological structure remains as the original network structure in dynamic process.The proposed architecture is implemented with C++ at System Level,and MPI parallel program is used to refactor the network for validation which ensures the correctness of the proposed module functions finally.

关 键 词：片上网络 重配置结构 MPSoC平台 M5模拟器 核级冗余 

分 类 号：TN402[电子电信—微电子学与固体电子学]