Complementary Pass-Transistor Adiabatic Logic Circuit Using Three-Phase Power Supply  

采用三相电源的互补传输管绝热逻辑电路(英文)

作　　者：胡建平[1] 邬杨波[1] 张卫强[1] 

机构地区：[1]宁波大学信息科学与工程学院,宁波315211

出　　处：《Journal of Semiconductors》2004年第8期918-924,共7页半导体学报（英文版）

基　　金：国家自然科学基金 (批准号 :60 2 73 0 93 );浙江省教育厅 (批准号 :2 0 0 10 2 3 8)资助项目~~

摘　　要：A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.提出了一种由三相电源驱动的新绝热逻辑电路—— complementary pass- transistor adiabatic logic (CPAL ) .电路由 CPL电路完成相应的逻辑运算 ,由互补传输门对输出负载进行绝热驱动 ,电路的整体功耗较小 .指出选取合适的输出驱动管的器件尺寸可进一步减小 CPAL电路的总能耗 .设计了仅由一个电感和简单控制电路组成的三相功率时钟产生电路 .为了验证提出的 CPAL电路和时钟产生电路 ,设计了 8bit全加器进行模拟试验 .采用 MO-SIS的 0 .2 5μm CMOS工艺 ,在 5 0～ 2 0 0 MHz频率范围内 ,CPAL全加器的功耗仅为 PFAL电路和 2 N - 2 N2 P电路的 5 0 %和 35 % .

关 键 词：complementary pass  transistor logic adiabatic logic low  power 3  phase power  clock generator 

分 类 号：TN432[电子电信—微电子学与固体电子学]