一种基于状态机的总线桥设计  

A bus bridge design based on finite state machine

作　　者：张振[1] 张溯[2] 

机构地区：[1]合肥工业大学计算机与信息学院,安徽合肥230009 [2]合肥工业大学电气与自动化工程学院,安徽合肥230009

出　　处：《合肥工业大学学报（自然科学版）》2004年第4期380-383,共4页Journal of Hefei University of Technology：Natural Science

基　　金：国家863重大专项基金资助项目(2002AA1Z1730);科技部重要技术标准研究专项资助项目(2002BA906A07)

摘　　要：随着半导体工艺技术的飞速发展,系统芯片SOC正逐渐成为集成电路设计中的主流发展趋势,基于IP重用的设计方法是提高SOC设计效率的有效途径。SOC设计通常采用层次化片上总线的体系结构,不同的IP集成在不同类型的总线上。为了实现SOC中集成在不同总线上的IP之间进行有效通信,可以采用设计总线桥的方法。文章提出了一种基于状态机的总线桥设计方法,设计结果通过了RTL功能验证。With the rapid development of semiconductor technology, the system on chip(SOC) has become the main trend of design of the integrated circuit(IC),and the Intellectual Property(IP) reuse-based design can improve the efficiency of designing the SOC. In the SOC design,the hierarchical on-chip-bus architecture is usually adopted,and different IPs are integrated on different types of buses. With the bus bridge,the communication between different IPs which integrated on different buses of the SOC can be realized. In the paper,a bus bridge design based on state machine is presented. The implementation has passed the register transfer(RT) level simulation.

关 键 词：:片上总线 总线桥 状态机 

分 类 号：TN402[电子电信—微电子学与固体电子学]