基于电热模拟的电迁移可靠性诊断及时钟完整性分析  

Electromigration reliability diagnosis and clock signal integrity analysis using electrothermal simulations

作　　者：王乃龙[1] 张盛[1] 周润德[1] 

机构地区：[1]清华大学微电子学研究所,北京100084

出　　处：《清华大学学报（自然科学版）》2004年第7期984-987,共4页Journal of Tsinghua University(Science and Technology)

基　　金：国家自然科学基金资助项目(59995550-01)

摘　　要：为诊断大规模集成电路设计过程中电迁移可靠性及分析时钟信号完整性,开发一种用于集成电路片上时钟信号模拟软件Etsim3。该模拟软件考虑了集成电路自热效应,通过电热耦合模拟以及金属连线温度分布解析模型获得更准确的集成电路芯片表面以及各金属连线网络上的温度分布。模拟结果表明,考虑集成电路自热效应前后,电迁移诊断以及时钟信号完整性分析结果都有了较大程度上的改变,Etsim3可以得到更为精确的分析以及诊断结果。Circuit reliability and clock signal integrity are very important constraints in VLSI (very large scale integration) circuit designs. This paper describes a new electromigration reliability diagnosis and clock signal integrity analysis tool (Etsim3) for VLSI circuits. Unlike previous reliability diagnosis and circuit performance analysis tools, Etsim3 can estimate the temperature distribution of the chip substrate and metal interconnects due to joule heating and heat conduction using electrothermal simulations with an analytical thermal model of the metal interconnections. Simulation results show that Etsim3 provides more accurate predictions of the chip substrate and metal interconnects temperatures including the self-heating effect of VLSI circuit chips. Etsim3 uses the temperature-dependent distributed RC interconnect delay model and the classical Black's equation to provide more accurate clock signal integrity analyses and electromigration reliability diagnosis results.

关 键 词：大规模集成电路 电热耦合模拟 时钟信号完整性 电迁移可靠性诊断 

分 类 号：TN47[电子电信—微电子学与固体电子学]