面向HDL描述基于路径覆盖的模拟矢量自动生成方法研究  

A New Method for Automatic Generating Simulation Vectors from HDL Descriptions Based-on Path Coverage

作　　者：李暾[1] 李思昆[1] )郭阳[1] 万海[2] 冷彪[1] 

机构地区：[1]国防科学技术大学计算机学院,长沙410073 [2]清华大学计算机科学与技术系,北京100084

出　　处：《计算机学报》2004年第6期721-728,共8页Chinese Journal of Computers

基　　金：国家自然科学基金 ( 60 3 0 3 0 11);国家自然科学基金重点项目基金( 90 2 0 70 19);国家"八六三"高技术研究发展计划项目基金 ( 2 0 0 2AA1Z14 80 )资助

摘　　要：提出和实现了一种面向HDL描述基于路径覆盖的模拟矢量自动生成方法 .该方法在约束生成时只考虑控制语句的条件表达式 ,可有效避免生成冗余约束 ;利用扩展的决策图模型解决了中间信号到初始输入的传播问题和信号依赖关系问题 ,以及处理各种HDL描述风格的问题 ;采用约束逻辑编程方法解决了由位、位向量和整型变量组成的约束系统的统一处理问题 .实验结果表明该方法能加快模拟矢量生成速度 ,提高路径覆盖率 .生成的模拟矢量也能用于低层次设计验证和故障模拟 ,加快了设计进度 .将该方法的原型系统用于一个 32位微处理器核RTL级验证 ,发现了RTL级设计描述中的错误 .A novel method for automatic generating simulation vectors from HDL descriptions based on path coverage and constraint solving is presented. The method only generates constraints for condition expression of the control statements, which can reduce the costs on constraint solving. It can deal with all constraints involving bits, bit-vectors and integers. It can deal with various HDL description styles, and various types of designs. Experimental results on several practical designs show that our method can efficiently improve the simulation vector generation process, which in turn accelerates the design process. The vectors generated by our method can also be used in low-level verification and fault simulation. The prototype system has been applied to verify RTL description of a real 32-bit microprocessor design and complex bugs remained hidden in the RTL descriptions are detected.

关 键 词：HDL描述 路径覆盖 模拟矢量自动生成 约束逻辑求解 VLSI 

分 类 号：TN47[电子电信—微电子学与固体电子学]