寄存器传输级低功耗设计方法  

RTL Low Power Design Methodology

作　　者：罗旻[1] 杨波[1] 高德远[1] 沈绪榜[1] 

机构地区：[1]西北工业大学航空微电子中心,陕西西安710072

出　　处：《小型微型计算机系统》2004年第7期1207-1211,共5页Journal of Chinese Computer Systems

摘　　要：随着移动设备需求量的不断增大和芯片工作速度的不断提高 ,芯片的功耗已经成为电路设计者必须考虑的问题 ,对于芯片整体性能的评估已经由原来的面积和速度的权衡变成面积、时序、可测性和功耗的综合考虑 ,并且功耗所占的权重会越来越大 .本文主要讲述在 RTL 设计中如何实现低功耗设计 .When more and more mobile equipments are needed and the frequency of chips is increased, the power of chips are more and more considered by designers. The evaluation of the total performance of chips is changed from areas and speed of chips to areas ,timing ,testability and power of chips ,and power will play more and more important role in the total performance.In this paper, we mainly discuss how to implement low power designs in RTL designs.

关 键 词：低功耗设计 寄存器传输级 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]