基于“有效电容”的RLC互连树延时分析  

Analysis of RLC interconnect tree delay based on "effective capacitance"

作　　者：董刚[1] 杨银堂[1] 李跃进[1] 

机构地区：[1]西安电子科技大学微电子研究所,陕西西安710071

出　　处：《西安电子科技大学学报》2004年第4期509-512,共4页Journal of Xidian University

基　　金：国家部委预研基金资助项目(41323020204)

摘　　要：在VLSI设计中,互连延时估计一直是很受关注的问题之一.提出了一种基于"有效电容"的RLC互连树延时分析的方法.把这种新方法与等效Elmore延时分析的方法做了仿真比较.结果显示,基于有效电容的RLC互连树延时分析方法误差要小于等效Elmore延时分析的方法.Interconnect delay evaluation is always a crucial concern in the VLSI design. An interconnect line in a VLSI circuit is in general a tree pattern rather than a single line. An approach to analyzing RLC interconnect tree delay based on effective capacitance is presented in this paper. This new method is compared with the equivalent Elmore delay, which shows that the relative error by the new method is less than that by the equivalent Elmore delay.

关 键 词：RLC互连树延时 有效电容 RLC互连Ⅱ模型 等效Elmore延时 

分 类 号：TN405.97[电子电信—微电子学与固体电子学]