基于BIST的FPGA逻辑单元测试方法  

An approach for testing FPGA logic cells based on BIST

作　　者：吴继娟[1] 孙媛媛 刘桂艳[2] 

机构地区：[1]哈尔滨工程大学计算机科学与技术学院,黑龙江哈尔滨150001 [2]东北轻合金有限责任公司铝品制造厂,黑龙江哈尔滨150040

出　　处：《哈尔滨工业大学学报》2004年第8期1074-1076,共3页Journal of Harbin Institute of Technology

基　　金：黑龙江省自然科学基金资助项目.

摘　　要：给出了一种基于内建自测(BIST)的测试现场可编程门阵列(FPGA)逻辑单元的方法,讨论了测试的配置结构、故障覆盖率和测试中出现的问题及解决办法.实验表明,该测试方法具有所需测试向量少、故障覆盖率高、简便适用等优点.An approach for FPGA(Field Programmable Gate Array) testing logic cells based on BIST(Built-In Self-Test) is presented. Some problems and corresponding solvent during testing, such as configurable structure and fault diagnose scale are discussed. Simulation results show that the testing approach have a lot of advantages, such as fewer test vectors, higher fault diagnose scale, a simple method of application, etc.

关 键 词：BIST FPGA 逻辑单元 现场可编程门阵列 内建自测 响应检验电路 故障覆盖率 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]