DSP中基于指令并行和任务并行的DMA接口设计  

A Instruction and Task parallel DMA Interface in DSP

作　　者：沈戈[1] 樊晓桠[1] 高德远[1] 段然[1] 

机构地区：[1]西北工业大学航空微电子中心,陕西西安710072

出　　处：《微电子学与计算机》2004年第7期160-163,共4页Microelectronics & Computer

基　　金：国家自然科学基金(60273088)

摘　　要：在面向多媒体数据流的计算密集型的应用中,不仅要求DSP(数字信号处理器)有非常强大的数据处理能力,还要求其具有高速的数据输入、输出接口带宽.本文在传统DSP常用的增强型哈佛结构的基础上,提出一种DSP处理器DMA接口结构的设计方案,实现了基于指令并行和任务并行的DMA并行传输模式.通过6个常用的DSP算法程序实验验证,在片上存储器使用单口RAM的前提下,指令中带有片上Memory访存操作的指令占总指令的42.2%～94.3%时,这种方法设计的DMA接口能够在DSP零开销的情况下,完成必要的数据传输.而且能够实现对Host处理器程序员透明的DMA数据传输操作,有效地提高了DSP系统的性能.In applications of the high data transfer ratio and high-density computing, such as communications, signal processing, multimedia systems etc., the programmable digital signal processors (DSPs) must not only be powerful in data processing, but also have higher bandwidth of input and output interface. Basing on Enhanced Harvard architecture, we propose a new design for DMA interface of DSPs, called DMA access and control mechanism based on dependence of data bus. New DMA interface supplies higher speed data transfer ratio and supports higher efficiency connecting to Host processors. In this paper, we evaluate the Enhanced Harvard architecture and new designed DMA interface using six assemble language source programs from ADI website. Experimental evidence is provided showing that the new designed DMA interface can transfer data while the DSP is continuing program execution, and for almost all applications, this design can improve DSP data processing capability and the data transfer speed of DMA interface. This architecture design technology still uses the single port RAM as it's on chip memory. New DMA interface also supports transparent data transmission for Host programmer.

关 键 词：DSP 处理器 DMA接口 并行 

分 类 号：TP368[自动化与计算机技术—计算机系统结构]