验证重用中的监视器设计  

The Design of Monitor for Verification Reuse

作　　者：杨羽[1] 张溯[1] 周萌[1] 詹文法[1] 

机构地区：[1]合肥工业大学微电子设计研究所,安徽合肥230009

出　　处：《微电子学与计算机》2004年第7期173-176,共4页Microelectronics & Computer

摘　　要：现代集成电路设计面临着一个困境,一方面是电路设计规模和复杂度的日益增加,另一方面则又面临着来自面市时间的巨大压力。在中等或大规模设计中验证工作往往占总开发工作量的70%以上,缩短验证时间可以有效提高设计的效率。采用基于事务的监视器搭建模块化验证平台,是实现缩短验证时间的有效手段。文中讨论了基于事务的监视器的基本工作原理和设计方法,并介绍了一个具体实例———总线监视器的设计。Modern IC design is faced with a dilemma. On the one hand, ASIC and SoC designs are getting more complex; on the other hand, the pressure from TTM is increased. Generally, verification process consumes over 70 percent of the design team's work. Decreasing verification time make design efficiency increased. Verification reuse methodology is a viable technique to decrease verification time. Transaction-based monitor is an important composition of reusable verification environment. This paper introduce the related theory and the design method of a monitor, then a real-world example ,bus monitor, is also proposed.

关 键 词：监视器 事务 重用 验证 SOC 

分 类 号：TN402[电子电信—微电子学与固体电子学]