基于并联开关技术的低电压nMOS数字电路开关级设计  

Design of Low-Voltage nMOS Digital Circuits at Switch-Level Based on Parallel Switches Technique

作　　者：姚茂群[1] 蒋征科[2] 黄志存 陈华华[2] 沈继忠[2] 

机构地区：[1]杭州师范学院信息学院,浙江杭州310012 [2]浙江大学信息与电子工程学系,浙江杭州310028 [3]杭州迪蒙电子技术有限公司,浙江杭州310012

出　　处：《科技通报》2003年第3期217-221,共5页Bulletin of Science and Technology

基　　金：浙江省科技厅重点资助项目(001110021);浙江省教育厅资助项目(教-6429811302)

摘　　要：在分析了采用低电压工作时数字电路性能下降甚至不能正常工作的原因后,提出了两种适合于低电压nMOS电路设计的串联开关转换成并联开关技术,并从开关级具体设计了低电压三值nMOS电路.对设计的电路进行模拟得到的结果表明,在采用标准工艺参数时,只要工作电压不低于管子阈值,则本文设计的低电压电路不仅具有正确的逻辑功能,而且具有较快的速度.The cause of the digital circuits performance reduction and even fail to operate at low supply voltage was analyzed, then, two methods for converting cascade switches to parallel switches which are suitable to design nMOS circuits at low voltage were proposed. Using these methods, several ternary nMOS circuits at low voltage with parallel switches were designed at switchlevel. Using the standard technology parameters, the simulation result using PSPICE showed that the designed circuits not only have the correct logic functions, but also have smaller propagation delay when the supply voltage is not lower than the threshold.

关 键 词：电子技术 集成电路 开关信号理论 低电压电路 多值电路 nMOS电路 并联开关 

分 类 号：TN431.2[电子电信—微电子学与固体电子学] TN402