基于FPGA的千兆硬件防火墙高速数据缓冲设计  

Study on high-speed data buffer design on gigabit hardware firewall based on FPGA

作　　者：王洁[1] 唐朔飞[1] 季振洲[1] 胡铭增[1] 

机构地区：[1]哈尔滨工业大学计算机科学与工程系,黑龙江哈尔滨150001

出　　处：《哈尔滨商业大学学报（自然科学版）》2004年第5期519-522,528,共5页Journal of Harbin University of Commerce：Natural Sciences Edition

基　　金："十五"国防预研项目(41316.3.3)

摘　　要：千兆硬件防火墙将在网络安全体系中起到非常重要的作用,数据缓冲是连接MAC与规则匹配和状态检测的枢纽.高速数据缓冲的良好设计是突破吞吐速率瓶颈的关键.提出了一种基于FPGA的千兆硬件防火墙高速数据缓冲的实现方法,订制并精简了WISHBONE总线互连的方式,提出MAC与数据缓冲数据透明的设计方案从而大大提高通讯性能,给出了利用FPGA的BLOCKRAM实现同步/异步FIFO的一般方法,提出延迟判定和数据预取的方式解决空满判定和串联BLOCKRAM访问时延问题.高速数据缓冲的设计具有一定的通用性.This paper put forward a method FPGA-based design of high-speed data buffer in gigabit hardware firewall, customs and simplifies the Interconnection of WISHBONE, put a scheme of increasing the data diaphaneity between MAC and data buffer, to greatly improve communication performance, provided a current method to realizing synchronous or asynchronous FIFO based upon BLOCK RAM of FGGA, gave the way of delay-check to find empty of full and the way of data prefetch to the problem of R/W delay of BLOCK RAM in series. The design of high-speed data buffer can be used in common currency.

关 键 词：数据缓冲 硬件防火墙 RAM 高速 预取 WISHBONE总线 规则匹配 FPGA 互连 MAC 

分 类 号：N09[自然科学总论—科学技术哲学] TP393.08[自动化与计算机技术—计算机应用技术]