MIPS系统中北桥的FPGA设计  

FPGA Design of North Bridge for MIPS System

作　　者：武杰[1] 乔崇[1] 张俊杰[1] 杜学峰[1] 唐世悦[1] 张万生[1] 王砚方[1] 

机构地区：[1]中国科学技术大学快电子实验室,安徽合肥230027

出　　处：《小型微型计算机系统》2004年第11期2028-2031,共4页Journal of Chinese Computer Systems

摘　　要：介绍了一个用 FPGA开发的用于 MIPS系统的北桥设计 ,主要包括北桥的结构框架、设计思想和技术特点等内容 ,并结合同类型的国外产品进行了性能上的比较和测试 。Described a FPGA design of north bridge for MIPS systems, the contents include the architecture and characters of the design. A new parallel system arbiter and SoC bus were used in the design. The arbiter was dual round-robin like, and can be programmed with different priority. Total equivalent gate count for design is 265,000, and it can work steadily at 83MHz clock (PCI clock is 33MHz). According the result of comparison with similar products, the north bridge achieves better or equal performance.

关 键 词：MIPS 北桥 WISHBONE总线 总线仲裁 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]