分数分频频率合成器的分数杂散抑制方法  

Fractional Spur Reduction Techniques in Fractional-N Frequency Synthesizer

作　　者：岳金山[1] 刘光祜[1] 

机构地区：[1]电子科技大学,四川省成都市610054

出　　处：《电子工程师》2004年第11期50-53,共4页Electronic Engineer

摘　　要：介绍了分数分频频率合成器的基本结构、原理、特点 ,着重分析分数杂散的产生机理和抑制方法。抑制分数杂散的方法很多 ,主要介绍D A转换估计法、随机抖动法、Δ ∑调制法、相位内插法、时延或相位补偿法、相位插入法 ,并对各种方法的优缺点进行了比较。The block scheme, principle and feature of a fractional-N frequency synthesizer are introduced in this paper. The mechanism of generating fractional spur and the fractional spur reduction technique are analyzed in detail. There are a lot of fractional spur reduction techniques. This paper is mainly concerned with DAC estimation ,random jittering, Δ-∑ modulation, phase interpolation, phase compensation and phase insertion. Since different techniques have different operation principles and each technique has its own advantages and disadvantages, it is impossible to discuss them in detail in this paper.

关 键 词：频率合成器 分数分频 分数杂散 杂散抑制 

分 类 号：TN74[电子电信—电路与系统]