Timing Optimization by Inserting Minimum Buffers with Accurate Delay Models  

精确时延模型下满足时延约束的缓冲器数目最小化的算法(英文)

作　　者：张轶谦[1] 洪先龙[1] 周强[1] 蔡懿慈[1] 

机构地区：[1]清华大学计算机科学与技术系,北京100084

出　　处：《Journal of Semiconductors》2004年第11期1409-1415,共7页半导体学报（英文版）

基　　金：国家自然科学基金 (批准号 :60 1760 16);国家高技术研究与发展计划 (批准号 :2 0 0 2 AAIZ14 60 )资助项目~~

摘　　要：An algorithm of minimizing the number of buffers under certain delay constraint with accurate delay models is presented.Given a two-terminal net,the algorithm can minimize the total number of buffers inserted to meet the delay constraint.A high order delay model is applied to estimate interconnect delay and a nonlinear delay model based on look-up table is for buffer delay estimation.The experimental results show that the algorithm can efficiently achieve the trade-offs between number of buffers and delay,and avoid needless power and area cost.The running time is satisfactory.提出了在精确时延模型下 ,满足时延约束的缓冲器数目最小化的算法 .给出一个两端线网 ,该算法可以求出满足时延约束的最小缓冲器数目 .运用高阶时延模型计算互连线的时延 ,运用基于查找表的非线性时延模型计算缓冲器的时延 .实验结果证明此算法有效地优化了缓冲器插入数目和线网的时延 ,在二者之间取得了较好的折中 .

关 键 词：buffer insertion interconnect optimization layout VLSI 

分 类 号：TP331[自动化与计算机技术—计算机系统结构]