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机构地区:[1]浙江大学物理系,杭州310031
出 处:《Journal of Semiconductors》2004年第11期1526-1531,共6页半导体学报(英文版)
摘 要:研究和设计了两种低功耗的 EPAL (efficient PAL )绝热开关电路 .这两种电路均采用逐级相位落后 90°的四相正弦功率时钟 .讨论了 EPAL电路的设计方法 ,并在不同时钟频率和不同的负载条件下用 1.2μm的 CMOS工艺参数对所设计的电路进行 PSPICE模拟 .模拟结果表明这两类电路均能完成正确的逻辑功能 .两种 EPAL的五级反相器 /缓冲器电路在功率时钟频率为 10 MHz时都比相应的 PAL - 2 N电路节省 80 %以上的功耗 ,在 4 0 0 MHz时功耗节省也分别可达 2 3%和 5 0 % .EPAL电路可以工作于更高的时钟频率 。Based on the causation analysis of shortage of PAL-2N circuits,two types of EPAL circuits are proposed.For cascading purpose,four sinusoidal clocks with 90° phase lag are employed.The design method of EPAL circuits is also discussed and the circuits designed by this method are simulated by PSPICE at different clock frequencies and loads using 1.2μm CMOS technology.Simulation results show that functions of EPAL circuits designed by this method are proved correct.For a 5bit shift register,power savings above 80% are achieved by two types of EPAL circuits,compared with PAL-2N circuit at 10MHz,and can reach 23% and 50% respectively at 400MHz.The power dissipations of EPAL circuits are obviously lower than that of PAL-2N homologous circuits.EPAL circuits can work at higher clock frequency and have larger load capacity and slighter distortion of their outputs.
分 类 号:TN432[电子电信—微电子学与固体电子学]
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