一种通用DSP单端口指令Cache设计  

A Mini Instruction Cache in a General Purpose DSP

作　　者：曾晓文[1] 陈杰[2] 胡访宇[1] 

机构地区：[1]中国科学技术大学电子工程与信息科学系,安徽合肥230027 [2]中科院微电子所,北京100029

出　　处：《微电子学与计算机》2004年第11期141-145,共5页Microelectronics & Computer

基　　金：国家863重点项目资助(2002AA1Z1130)

摘　　要：在一款采用改进HARVARD总线结构的通用DSP中,通过设置一个小型指令CACHE来缓解流水线上的资源冲突。它采用两路组相连结构,仅在流水线上发生资源冲突时才会被访问。出于减小CACHE的面积和功耗考虑,该CACHE采用了单地址端口的设计,也就意味着在同一时钟周期内,CACHE只能完成一次读或写的操作。当读写请求同时发生的时候,必须采用一定的优先策略。本文结合DSP的结构特点,对一些优先策略进行了分析,最后对比了各种策略所付出的代价以及在一些benchmark下的性能。从结果可以看出,通过采取某些策略,该单端口指令CACHE可以获得与双端口CACHE几乎相同的命中率。In a general purpose DSP which is based on modified harvard architecture, a small instruction cache is adopted to alleviate the resource conflict in the pipeline. It's accessed not in every clock cycle, but when conflicts happen in the pipeline. For the purpose of minimizing its area and power dissipation, the instruction cache has single address port, which means in the same clock cycle only one operation of load or store can be realized. So some priority strategies should be applied if requests of reading and writing cache come at the same time. In this paper four strategies are presented and analyzed. According to the result of simulations under some benchmarks, the instruction cache using certain strategy may achieve almost the same hit rate with a dual-port one.

关 键 词：DSP流水线 CACHE冲突 策略 

分 类 号：TN4[电子电信—微电子学与固体电子学]