哈佛体系结构的Cache控制器设计  

Design of Cache Controller with Harvard Architecture

作　　者：谢学军[1] 叶以正[1] 王进祥[1] 喻明艳[1] 

机构地区：[1]哈尔滨工业大学微电子中心,哈尔滨150001

出　　处：《计算机工程》2004年第22期37-39,共3页Computer Engineering

基　　金：国防科研基金资助项目

摘　　要：对所设计的Cache控制器的地址映像、Cache Memory的访问流程以及Cache的替换算法和写策略进行了介绍,并分析了IU与Cache控制器的一致性及猝发访问的产生等设计中的关键问题。该设计已嵌入到Lilac 系统的设计中,通过了FPGA原型验证并用TSMC 0.25μm CMOS工艺流片。The paper presents the cache controller from following aspect: the address-mapping, the cache accessing flow, the replaced algorithm and the policy on write misses. The key issues in design, such as how to keep the consistency between the IU and cache and how to produce a burst memory accessing, are also analyzed in the paper. The cache controller has been embedded into Lilac system which verified by FPGA and manufactured using TSMC 0.25μmCMOS technology.

关 键 词：计算机 体系结构 哈佛体系结构 CACHE 控制器 设计 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]